1. Field of the Invention
The present invention relates to operating methods for electrically programmable and erasable non-volatile memory and integrated circuits including such memory, and more particularly to methods for establishing low threshold states and for correction and prevention of over-erase conditions in such devices.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names NROM, SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
One problem associated with EEPROM and flash memory cells is known as over-erase. The over-erase condition occurs when a biasing arrangement is applied to lower the threshold of the memory cell, where the low threshold state is considered the erase state of the cell. If the biasing arrangement establishes an amount of negative charge trapped in the charge storage element that is too low, then the threshold voltage of the memory cell will be too low, and the memory cell can leak current. Leakage current can interfere with successful operation of a memory array. The over-erase condition is one problem that has limited the scaling of charge trapping memory cell structures in the prior art.
Accordingly, it is desirable to provide an operating method for charge trapping memory cell structures in which over-erase is prevented.